datel, inc., 11 cabot boulevard, mansfield, ma 02048 (u.s.a.) ? tel: (508)339-3000, (800)233-2765 fax: (508)339-6356 ? email: datellit@mcimail.com features ? 16-bit resolution ? 500khz sampling rate ? functionally complete ? excellent dynamic performance ? 83db snr, ?89db thd ? no missing codes ? small, 40-pi n, tdip package ? 3.5 watts power dissipation ? on-board fifo 16-bit, 500khz sampling a/d converters ads-930 ? ? innov a tion and ex cellence general description the low-cost ads-930 is a high-performance, 16-bit, 500khz sampling a/d converter. this device accurately samples full- scale input signals up to nyquist frequencies with no missing codes. the dynamic performance of the ads-930 is optimized to achieve a thd of ?89db and an snr of 83db. packaged in a small, 40-pin, ceramic tdip, the functionally complete ads-930 contains a fast-settling sample-hold amplifier, a subranging (three-pass) a/d converter, an internal reference, an on-board fifo, timing and control logic, three- state outputs and error-correction circuitry. digital inputs/ outputs are ttl. requiring 15v and +5v supplies, the ads-930 typically dissipates 3.5 watts. the unit is offered with a bipolar input range of 5v or a unipolar i nput range of 0 to ?10v. models are available for use in either commercial (0 to +70c) or military (?55 to +125c) operating temperature ranges. typical applications include rada r, sonar, medical/graphic imaging, and fft spectrum analysis. figure 1. ads-930 functional block diagram pin function pin function 1 +10v ref. out 40 bit 1 (msb) 2 bipolar 39 bit 1 (msb) 3 analog input 38 bit 2 4 analog ground 37 bit 3 5 offset adjust 36 bit 4 6 gain adjust 35 bit 5 7 +15v supply 34 bit 6 8 comp. bits 33 bit 7 9 enable 32 bit 8 10 fifo read 31 bit 9 11 analog ground 30 analog ground 12 ?15v supply 29 bit 10 13 analog ground 28 bit 11 14 overflow 27 bit 12 15 eoc 26 bit 13 16 +5v supply 25 bit 14 17 start convert 2 4 digital ground 18 digital ground 23 fifo/dir 19 fstat1 22 bit 15 20 fstat2 21 bit 16 (lsb) input/output connections 3-state output register 40 bit 1 (msb) 39 bit 1 (msb) 38 bit 2 37 bit 3 36 bit 4 35 bit 5 34 bit 6 33 bit 7 32 bit 8 31 bit 9 29 bit 10 28 bit 11 27 bit 12 26 bit 13 25 bit 14 22 bit 15 21 bit 16 (lsb ) timing and control logic gain adjust 6 +10v ref. out 1 offset adjust 5 eoc 15 +5v supply +15v supply ?15v supply analog ground digital ground custom gate array power and grounding 3-pass analog-to-digital converter s/h gain adjust ckt. offset adjust ckt. precision +10v reference analog input 3 start convert 17 comp. bits 8 19 fstat1 20 fstat2 23 fifo/dir 10 fifo read 9 enable 14 overflow 16 7 12 4, 11, 13, 30 18, 24 bipolar 2
ads-930 2 ? ? +25c 0 to +70c ?55 to +125c analog inputs min. typ. max. min. typ. max. min. typ. max. units input voltage range bipolar ? 5 ? ? 5 ? ? 5 ? volts unipolar ? 0 to ?10 ? ? 0 to ?10 ? ? 0 to ?10 ? volts input resistance 1.4 1.5 1.7 1.4 1.5 1.7 1.4 1.5 1.7 k input capacitance ? 7 15 ? 7 15 ? 7 15 pf digi tal inputs logic levels logic "1" +2.0 ? ? +2.0 ? ? +2.0 ? ? volts logic "0" ? ? +0.8 ? ? +0.8 ? ? +0.8 volts logic loading "1" ? ? +20 ? ? +20 ? ? +20 a logic loading "0" ? ? ? ?20 ? ? ?20 ? ? ?20 a start convert positive pulse width ? 175 200 215 175 200 215 175 200 215 ns static performance resolution ? 16 ? ? 16 ? ? 16 ? bits integral nonlinearity (f in = 10khz) ? 1.0 ? ? 1.5 ? ? 2.0 ? lsb differential nonlinearity (f in = 10khz) ? 0.75 ? ? 1.0 ? ? 1.5 ? lsb full scale absolute accuracy ? 0.05 0.18 ? 0.2 0.5 ? 0.5 0.8 %fsr unipolar zero error (tech note 2) ? 0.05 0.085 ? 0.1 0.25 ? 0.25 0.5 %fsr bipolar zero error (tech note 2) ? 0.05 0.085 ? 0.15 0.25 ? 0.25 0.5 %fsr bipolar offset error (tech note 2) ? 0.05 0.15 ? 0.1 0.25 ? 0.25 0.5 %fsr gain error (tech note 2) ? 0.1 0.15 ? 0.15 0.35 ? 0.25 0.65 % no missing codes (f in = 10khz) 16 ? ? 16 ? ? 15 ? ? bits dynamic performance peak harmonics (?0.5db) dc to 100khz ? ?91 ? ? ?91 ? ? ?87 ? db 100khz to 250khz ? ?86 ? ? ?86 ? ? ?84 ? db total harmonic distortion (?0.5db) dc to 100khz ? ?89 ?81 ? ?89 ?81 ? ?85 ?76 db 100khz to 250khz ? ?84 ? ? ?84 ? ? ?82 ? db signal?to?noise ratio (w/o distortion, ?0.5db) dc to 100khz 81 83 ? 81 83 ? 75 80 ? db 100khz to 250khz ? 80 ? ? 80 ? ? 79 ? db signal?to?noise ratio ? (& distortion, ?0.5db) dc to 100khz 78 81 ? 77 81 ? 72 78 ? db 100khz to 250khz ? 78 ? ? 78 ? ? 76 ? db two?tone intermodulation distortion (f in = 100khz, 240khz, f s = 500khz, ?0.5db) ? ?82 ? ? ?82 ? ? ?81 ? db noise ? 150 ? ? 150 ? ? 150 ? vrms input bandwidth (?3db) small signal (?20db input) ? 2 ? ? 2 ? ? 2 ? mhz large signal (?0.5db input) ? 1.1 ? ? 1.1 ? ? 1.1 ? mhz feedthrough rejection (f in = 250khz) ? 92 ? ? 92 ? ? 92 ? db slew rate ? 80 ? ? 80 ? ? 80 ? v/s parameters limits units +15v supply (pin 7) 0 to +16 volts ?15v supply (pin 12) 0 to ?16 volts +5v supply ( pin 16) 0 to +6 volts digital inputs (pin 8, 9, 10, 17, 23) ?0.3 to +v dd +0.3 volts analog input (pin 3) unipolar ?12.5 to +12.5 volts bipolar ?7.5 to +12.5 volts lead temperature (10 seconds) +300 c parameters min. typ. max. units operating temp. range, case ads-930mc 0 ? +70 c ADS-930MM ?55 ? +125 c thermal impedance jc ? 4 ? c/watt ca ? 18 ? c/watt storage temperature range ?65 ? +150 c package type 40-pin, metal-sealed, ceramic tdip weight 0.56 ounces (16 grams) absolute maximum ratings physical/environment al functional specifications (t a = +25c, v cc = 15v, +v dd = +5v, 500khz sampling rate, and a minimum 5 minute warmup ? unless otherwise specified.)
ads-930 ? ? 3 +25c 0 to +70c ?55 to +125c dynamic performance (cont.) min. typ. max. min. typ. max. min. typ. max. units aperture delay time ? 10 ? ? 10 ? ? 10 ? ns aperture uncertainty ? 5 ? ? 5 ? ? 5 ? ps rms s/h acquisition time ( to 0.003%fsr, 10v step) ? 460 545 ? 460 545 ? 460 545 ns overvoltage recovery time ? 600 1000 ? 600 1000 ? 600 1000 ns a/d conversion rate 500 ? ? 500 ? ? 500 ? ? khz analog output internal reference voltage +9.95 +10.0 +10.05 +9.95 +10.0 +10.05 +9.95 +10.0 +10.05 volts drift ? 10 ? ? 10 ? ? 10 ? ppm/c external current ?? 1 ??1 ?? 1ma digi tal outputs logic levels logic "1" +2.4 ? ? +2.4 ? ? +2.4 ? ? volts logic "0" ? ? +0.4 ? ? +0.4 ? ? +0.4 volts logic loading "1" ? ? ?4 ? ? ?4 ? ? ?4 ma logic loading "0" ? ? +4 ? ? +4 ? ? +4 ma delay, falling edge of enable to output data valid ? ? 10 ? ? 10 ? ? 10 ns output coding complementary offset binary; complementary two's complement, offset binary, two's complement power requirements power supply ranges +15v supply +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 volts ?15v supply ?14.5 ?15.0 ?15.5 ?14.5 ?15.0 ?15.5 ?14.5 ?15.0 ?15.5 volts +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.75 volts power supply currents +15v supply ? +110 +130 ? +110 +130 ? +110 +130 ma ?15v supply ? ?100 ?125 ? ?100 ?125 ? ?100 ?125 ma +5v supply ? +80 +90 ? +80 +90 ? +80 +90 ma power dissipation ? 3.5 4.25 ? 3.5 4.25 ? 3.5 4.25 watts power supply rejection ? ? 0.02 ? ? 0.02 ? ? 0.02 %fsr/%v technical notes 1. obtaining fully specified performance from the ads-930 requires careful attention to pc-card layout and power supply decoupling. the devi ce's analog and digital ground systems are connected to each other internally. for optimal performance, tie all ground pins (4, 11, 13, 18, 24 and 30) directly to a large analog ground plane beneath the package. bypass all power supplies and the +10v reference output to ground with 4.7f tantalum capacitors in parallel with 0.1f ceramic capacitors. locate the bypass capacitors as close to the unit as possible. 2. the ads-930 achieves its specified accuracies without the need for external calibration. if required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in figure 2. when using this circuitry, or any similar offset and gain calibra- tion hardware, make adjustments following warmup. to avoid interaction, always adjust offset before gain. tie pins 5 and 6 to analog ground (pin 4) if not using offset and gain adjust circuits. footnotes: ? all power supplies must be on before applying a start convert pulse. all supplies and the clock (start convert) must be present during warmup periods. the device must be continuously converting during this time. ? when comp. bits (pin 8) is low, logic loading "0" will be ?350a. ? a 200ns wide start convert pulse is used for all production testing. for applications requiring less than a 500khz sampling rate, wider start convert pulses can be used. ? effective bits is equal to: 6.02 (snr + distortion) ? 1.76 + 20 log full scale amplitude actual input amplitude 3. pin 8 (comp. bits) is used to select the digital output coding format of the ads-930. see tables 3a and 3b. when this pin has a ttl logic "0" applied, it complements all of the ads-930's digital outputs. when pin 8 has a logic "1" applied and the ads-930 is operated within its unipolar (0 to ?10v) input range, the output coding is straight binary. applying a logic "0" to pin 8 under these conditions changes the output coding to complemen- tary binary. when pin 8 has a logic "1" applied and the ads-930 is operated within its bipolar (5v) i nput range, the output coding is offset binary. applying a logic "0" to pin 8 under these conditions changes the coding to complementary offset binary. using the msb output (pin 40) instead of the msb output (pin 39) under these conditions changes the respective output codings to two's complement and complementary two's complement. pin 8 is ttl-compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. there is an internal pull-up resistor on pin 8 allowing
ads-930 4 ? ? delay pin transition min. typ. max. units direct mode to fifo enabled 23 ? 10 20 ns fifo enabled to direct mode 23 ? 10 20 ns fifo read to output data valid 10 ? ? 40 ns fifo read to status update when changing from ads-930 ? ? 5 ?9.999847 ?9.999771 ?8.750000 ?7.500000 ?5.000000 ?4.999924 ?2.500000 ?1.250000 ?0.000153 ?0.000076 0.000000 1111 1111 1111 1111 lsb "1" to "0" 1110 0000 0000 0000 1100 0000 0000 0000 1000 0000 0000 0000 0111 1111 1111 1111 0100 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0001 lsb "0" to "1" 0000 0000 0000 0000 comp. off. bin. 0000 0000 0000 0000 lsb "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 0000 0000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 lsb "1" to "0" 1111 1111 1111 1111 offset binary 0111 1111 1111 1111 lsb "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 lsb "0" to "1" 1000 0000 0000 0000 comp. two's comp. 1000 0000 0000 0000 lsb "0" to "1" 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 1111 1111 1111 0101 1111 1111 1111 0111 1111 1111 1110 lsb "1" to "0" 01111111 1111 1111 two's comp. +4.999847 +4.999771 +3.750000 +2.500000 0.000000 ?0.000076 ?2.500000 ?3.750000 ?4.999847 ?4.999924 ?5.000000 +fs ?1 lsb +fs ?1 1/2 lsb +3/4 fs +1/2 fs 0 ?1/2 lsb ?1/2 fs ?3/4 fs ?fs +1 lsb ?fs + 1/2 lsb ?fs ?fs +1 lsb ?fs +1 1/2 lsb ?7/8 fs ?3/4 fs ?1/2fs ?1/2fs ?1/2lsb ?1/4fs ?1/8fs ?1 lsb ?1/2lsb 0 unipolar input output coding input bipolar scale range range scale 0 to ?10v msb lsb msb lsb msb lsb msb lsb 5v straight bin comp. binary table 3b. output coding calibration procedure (refer to figure 2 and tables 3a, and 3b) connect the converter per table 2 for the appropriate input voltage range. any offset/gain calibration procedures should not be implemented until the device is fully warmed up. to avoid interaction, adjust offset before gain. the ranges of adjustment for the circuits in figure 2 are guaranteed to compensate for the ads-930's initial accuracy errors and may not be able to compensate for additional system errors. a/d converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. this is accomplished by connecting led's to the digital outputs and performing adjustments until certain led's "flicker" equally between on and off. other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. for the ads-930, offset adjusting is normally accomplished when the analog input is 0 minus ? lsb (?76v). see table 3b for the proper bipolar and unipolar output coding. gain adjusting is accomplished when the analog input is at nominal full scale minus 1? lsb's (?9.999771v for unipolar and +4.999771v for bipolar). note: connect pin 5 to analog ground (pin 4) for operation without zero/offset adjustment . connect pin 6 to pin 4 for operation without gain adjustment. zero/offset adjust procedure 1. apply a train of pulses to the s tart convert input (pin 17) so that the converter is continuously converting. 2. for unipolar or bipolar zero/offset adjust, apply ?76.3v to the analog input (pin 3). figure 2. bipolar connection diagram table 3a. setting output coding selection (pin 8) straight binary 1 complementary binary 0 complementary offset binary 0 offset binary 1 complementary two?s complement 0 (using msb, pin 40) two?s complement 1 (using msb, pin 40) output format pin 8 logic level 3. for a bipolar input - adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 8 tied high (offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 8 tied low (complementary offset binary). for a unipolar input - adjust the offset potentiometer until all output bits are 0's and the lsb flickers between 0 and 1 with pin 8 tied high (straight binary) or until all output bits are 1's and the lsb flickers between 0 and 1 with pin 8 tied low (complementary binary). 4. two's complement coding requires using bit 1 (msb) (pin 40). with pin 8 tied high, adjust the trimpot until the output code flickers between all 0's and all 1's. table 2. input connections 0 to ?10v pin 3 pins 2 and 4 5v pin 3 pins 1 and 2 input range input pin tie together ads-930 20k 15 14 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 22 21 eoc overflow bit 1 (msb) bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 (lsb) analog ground digital ground 0.1f 4.7f 0.1f comp. bits 4.7f +10v ref. out fifo read 16 18, 24 8 1 10 +5v digital ?15v +15v offset adjust gain adjust 5 6 3 0.1f 4.7f 4, 11 13, 30 12 0.1f 4.7f 7 ++ 20k ?15v +15v ?15v +15v 17 start convert analog input 9 enable 23 fifo/dir 19 fstat1 2 bipolar 20 fstat2 +5v +5v +15v ? 15v
ads-930 6 ? ? gain adjust procedure 1. apply +4.999771v to the analog input (pin 3) for bipolar gain adjust or apply ?9.999771v to pin 3 for unipolar gain adjust. 2. for a unipolar input - adjust the gain potentiometer until all output bits are 1's and the lsb flickers between a 1 and 0 with pin 8 tied high (straight binary) or until all output bits are 0's and the lsb flickers between a 1 and 0 with pin 8 tied low (complementary binary). for a bipolar input - adjust the gain potentiometer until all output bits are 1's and the lsb flickers between a 1 and 0 with pin 8 tied low (complementary offset binary) or until all output bits are 0's and the lsb flickers between a 1 and 0 with pin 8 tied high (offset binary). 3. two's complement coding requires using pin 40. with pin 8 tied high, adjust the gain trimpot until the output code flickers equally between 1000 0000 0000 0000 and 1000 0000 0000 0001. thermal requirements all datel sampling a/d converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70c and ?55 to +125c. all room-temperature (t a = +25c) production testing is performed without the use of heat sinks or forced-air cooling. thermal impedance figures for each device are listed in their respective specification tables. these devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. the ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. electrically- insulating, thermally-conductive "pads" may be installed underneath the package. devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. in more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of datel's hs series heat sinks. see ordering information for the assigned part number. see page 1-183 of the datel data acquisition components catalog for more information on the hs series. request datel application note an-8, "heat sinks for dip data converters," or contact datel directly, for additional data. figure 4. fft analysis of ads-930 figure 3. ads-930 timing diagram note: scale is approximately 50ns per division. start convert internal s/h n 10ns min., 25ns max. eoc output data data n-1 valid hold 1.54s typ. 140ns max. data n valid 1.39s min. invalid data 460ns typ. 545ns max. acquisition time 10ns min. 25ns max. conversion time 700ns 30ns 175ns min., 200ns typ., 215ns max . n+1 780ns 30ns 30ns min .
ads-930 ? ? 7 figure 5. ads-930 evaluation board schematic. 0.1mf 74hct373 .22mf 0.1mf 0.1mf 0.1mf 0.22mf 0.1mf 0.1mf .1mf 2.2mf 2.2mf 2.2mf 20k 20k 74hct86 74hct373 2.2mf 0.1mf 74hct 123 33pf 20k 74hct86 15k 74hct86 2mh 74hct86 p1-7 p1-9 p1-11 u1-10 u1-9 u1-8 74hct373 ads-930 2. sg1-sg3 are initially open. width pulse gain offset (see note 1) 1. c14 & c15 should be 16v or greater. notes: +5v enbl 8q 7q 6q 5q 4q 3q 2q 1q ltch 8d 7d 6d 5d 4d 3d 2d 1d +5v +5v +5v +5v agnd dgnd dgnd agnd agnd agnd b9 b8 b7 b6 b5 b4 b3 b2 b1 b1 b16 b15 dir b14 b13 b12 b11 b10 ref b.p. anain offset gain +15v compb enb read -15v o.f. eoc +5v trig fs1 fs2 +15v +15v +15v +15v -15v -15v -15v -15v +5v +5v enbl 8q 7q 6q 5q 4q 3q 2q 1q ltch 8d 7d 6d 5d 4d 3d 2d 1d +5v +5v enbl 8q 7q 6q 5q 4q 3q 2q 1q ltch 8d 7d 6d 5d 4d 3d 2d 1d +5v 34 32 30 28 26 24 22 20 33 6 8 10 12 14 16 18 31 27 29 23 25 19 21 3 5 7 9 11 13 15 17 1 2 4 1 2 3 4 7 8 13 14 17 18 11 10 20 2 5 6 9 12 15 16 19 1 1 2 1 2 12 1 2 1 2 1 2 + + + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 5 6 43 87 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 1 2 3 1 2 3 1 2 3 7 14 3 4 7 8 13 14 17 18 11 10 20 2 5 6 9 12 15 16 19 1 + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 12 13 11 4 5 6 9 10 8 3 4 7 8 13 14 17 18 11 10 20 2 5 6 9 12 15 16 19 1 1 2 1 2 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 sg1 j13 j15 j3 c12 u2 c7 c11 c10 c9 c8 c5 c1 c3 c6 c2 c4 u1 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 r2 r1 u5 u4 c15 c14 j4 u6 c13 r3 j18 j17 j16 u5 r4 u5 j6 j5 l1 u5 j7 j10 j1 j14 j2 j9 u3 j12 j8 j11 sg2 p4 sg3 o.f. b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 t rigger trig b3 b2 b1 eoc analog input b1 fs1 fs2 enable dir read enb compb (lsb) (msb) p3
ads-930 mechanical dimensions inches (mm) ordering inform ation oper ating analog model number tem p. range input ads-930mc 0 to +70c 0 to ?10v, 5v ADS-930MM ?55 to +125c 0 to ?10v, 5v receptacles for pc board mounting can be ordered through amp, inc., part # 3-331272-8 (component lead socket), 40 required. for mil-std-883 product, or surface mount packaging, contact d atel. accessories ads-e val3 evaluation board (without ads-930) hs-40 heat sink for all ads-930 models pin 1 index ( on top) 2.12/2.07 (53.85/52.58) 0.018 0.002 (0.457) 0.100 typ. (2.540) 0.110/0.090 (2.794/2.286) seating plane 0.035/0.015 (0.889/0.381) 0.200/0.175 (5.080/4.445) 0.245 max. (6.223) 0.210 max. (5.334) 0.045/0.035 (1.143/0.889) 1.11/1.08 (28.20/27.43) 120 21 40 1.900 0.008 (48.260) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.015/0.009 (0.381/0.229) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286 ds-0307pb 3/97 ?? innov a tion and ex cellence datel makes no representation that the use of its products in the circuits described herein, or the use of other technical info rmation contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are s ubject to change without notice. the datel l ogo is a registered datel, inc. trademark. i so 900 1 iso 9001 registered datel (uk) ltd. tadley, england t el: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 01-34-60-01-01 datel gmbh mnchen, germany t el: 89-544334-0 datel kk t okyo, japan tel: 3-3779-1031, osaka tel: 6-354-2025 datel, inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 email: datellit@mcimail.com data sheet fax back: (508) 261-2857 ? ?
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